Marco Volpini

Marco Volpini

ElectricalEngineering

3rd year @ WaterlooOpen to Winter 2027 co-op

Explore projectsContact Marco
Low-angle render of the AILED high-voltage safety board Marco designed: a black PCB with a Coilcraft flyback transformer, film capacitors and a fuse
I designed this boardAILED · UW Formula ElectricRendered from my Altium filesSee the build
Featured projects

Featured builds.

DriveWire Telemetry thumbnail

DriveWire Telemetry

Active mini EV platform: a custom 2S LiPo power PCB with both buck converters designed in Altium, ESP32-S3 FreeRTOS firmware proven on the bench, and stall-current measurements driving the design.

AltiumESP32-S3FreeRTOS
Explore build
Formula Electric AILED thumbnail

Formula Electric AILED

Ground-up redesign of the accumulator indicator safety board. The 588 V tractive bus itself powers an isolated 12 V indicator: no GLV, no software.

588 VTractive bus
57.4 VTrip point
12.7 mmCreepage
AltiumIsolated flybackHV safety
Explore build
Custom 6T SRAM Bit Cell thumbnail

Custom 6T SRAM Bit Cell

Transistor-level bit cell with grounded-gate PMOS loads: SPICE-validated, laid out in Magic VLSI on Sky130, and taped out at 51.69 µm².

SPICESky130Taped out
Explore build
RV32I datapath progressBuilt: a 32-bit program counter that resets to 0x01000000 and adds 4 each cycle, byte-addressable little-endian instruction memory, a combinational decoder with immediate generation, a 32 by 32-bit register file with two read ports and one write port, and a combinational ALU that also resolves branches, instrumented with 21 probes. Next: data memory and write-back.BUILT · FETCH TO ALUNEXT · WRITE-BACK+4PC32-bitreset0x01000000imemorybyte-addrlittle-endian1 MiBpcinsndecodeR I S B U Jimm gen5 layouts9 probesrs1rs2rdimmreg file32 x 32-bit2R · 1WALU+ branch6 conditionsdata memload/storewrite-backto rdbuilt: fetch · decode · reg file · ALUnext: write-back21 probes

RISC-V Processor in RTL

32-bit RV32I processor in Verilog, built stage by stage. Fetch, a six-format decoder, a 32-register file, and the ALU with branch logic are in RTL and checked against golden traces in Verilator. Write-back is next.

VerilogVerilatorIn progress
View progress
Conceptual diagram for RF Low-Noise Amplifier

RF Low-Noise Amplifier

Designing a microwave LNA and impedance-matching networks in Keysight ADS. Microstrip layout, fabrication, assembly, and measurement are planned.

RF designKeysight ADSIn progress
Case study coming soon
Wireframe drawing of the custom DriveWire support stand CAD model
DriveWire support stand · SolidWorks CAD
Experience

Engineering experience.

May 2026 - Present

UW Formula Electric

Electrical Design Engineer

588 VTractive bus
4.7 kVHipot rating (rms)
12.7 mmCreepage

Designed the accumulator indicator board from schematic through PCB layout, with an isolated 12 V indicator powered by the tractive bus itself. No GLV, no software.

Altium · Flyback · HV isolationAILED build
Jan 2026 - May 2026

Eaton

Power Systems Engineering Intern

20+Distribution systems
44 kVMax system voltage
30%+Less reporting time

Short circuit, arc flash, and protective device coordination studies in SKM PowerTools, plus Power BI dashboards used by the whole PSE team.

SKM PowerTools · SLDs · Power BI
Earlier
Sep 2024 - Jan 2025
G. L. Tiley & AssociatesHoist Control and Automation Assistant

Wired, traced, and reviewed Studio 5000 ladder logic, HMI screens, and electrical schematics across SIL safety standards, cross-checking I/O and device tags.

Jan 2024 - May 2024
RTG SystemsEngineering Design Assistant

Prepared 20+ AutoCAD drawing packages for EV charging, traffic signalization, hydro, and street lighting infrastructure.

Sep 2023 - May 2024
WaterloopPropulsion, Electrical and Firmware Team Member

Thermistor temperature sensing for the linear induction motor, with PCB design and C firmware.

Skills

Technical toolkit.

Marco Volpini
Ski instructor · swimmer · drummer

Let's build something.

I'm looking to join hardware, silicon, power electronics, embedded, and vehicle teams.

Email MarcoDownload resumeView LinkedInView GitHub

marcoavolpini@gmail.com